As a reconfigurable logic (Reconfigurable Logic), which is rewritable logic device, various devices have been proposed and put into practical use. A field programmable gate array (Field Programmable Gate Array: FPGA) where basic logic blocks are arranged on a semiconductor chip in an array to allow reconfiguration of logic, has been put into practical use, as an example of a reconfigurable logic.
As an example of the FPGA, Patent Literature 1 (JP Patent Kokai Publication No. JP-H09-148440A), for example, discloses a variable logic integrated circuit, in which a plurality of variable logic blocks each configured to enable a change of its logic function, and a plurality of variable wiring circuits each configured to enable interconnection between any of the variable logic blocks are alternately arranged on a semiconductor chip in transverse and vertical directions and a wiring arrangement that is not connected to the variable logic blocks but is to be used for a different purpose is formed above the variable logic blocks.
As another related art, Patent Literature 2 (JP Patent Kokai Publication No. JP2006-32951A), for example, discloses a single polarity-type resistance variable PCMO register adjusting circuit comprising a resistance bridge circuit network and a pulse feed-back circuit, wherein the resistance bridge circuit network includes a reference register and a matching register which is formed of a programmable resistance material having a single polarity-type resistance variable characteristic, wherein the resistance bridge circuit network compares resistance states of the reference register and the matching register and then generates a comparison signal indicating a difference between the resistance states, and wherein the pulse feed-back circuit is connected to the resistance bridge circuit network, supplies an electric pulse signal of a single polarity according to the comparison signal in order to correct the resistance value of the matching register with respect to the resistance value of the reference register, and reversibly adjusts the resistance value of the matching register with respect to the resistance value of the reference register.
[PTL 1]
    JP Patent Kokai Publication No. JP-H-9-148440A[PTL 2]    JP Patent Kokai Publication No. JP2006-32951A